1. Microprocessor and Interfacing Techniques SE Computer Engineering April/May 2014

Q.1 (a) What are the different component of MS-DOS? Explain DOS loading with the help of neat diagram


MS-DOS is created using following three files.




These files are created for special purpose like  creating, booting and coordinating with devices for input, output  and saving internal commands of DOS in memory.In other words these are program files which are created which creating DOS.

IO.SYS: These two files are hidden files. These are system files and are present on every disc. At the time of booting both of these Files are automatically get saved in Temporary Memory. IO.sys stores the standard operation related to input and output devices. And MSDOS.sys file stores command that contact with operating system.

COMMAND.COM :This is a command interpreter file in MS-DOS which is a group of IO.sys, MSDOS.sys and COMMAND.COM. At the time of booting of computer, all these three files are automatically saved in the memory. COMMAND.COM file contains all the definitions of Internal command and programs of these commands. This file is mainly responsible for executing command which are typed by user in command prompt.

AUTOEXE.BAT: After booting Operating System it looks for AUTOEXE.BAT file in the disc and executes it. This process is repeated when computer is switched on. It is a batch file which contains MS-DOS command like a program file and it automatically executes the command written in it. Therefore it is named AUTOEXE.BAT which means self executable batch file. BIOS is a set of basic instructions and drivers for the monitor, keyboard, printer, I / O ports and other devices in the PC configurations. The task of the BIOS is to mediate between the demands of the remaining parts of the OS and all of these devices. BIOS each OS translates the request into a series of instructions that the microprocessor controlled devices. Many manufacturers expand content BIOS variety of additional features, such as antivirus software, since current technology allows, but for correct operation must not disturb the base that must be the same as the IBM BIOS. When the BIOS enables the microprocessor to make contact with the disk (partition) on which the operating system, the command for copying files to the following picture.

New Bitmap Image (5)

MSDOS.SYS and IO.SYS form the CORE of the operating system. Group DBLSPACE.??? used when the data is compressed on disk. COMMAND.COM is INTERPRETER (simultaneous interpreter) command, which the user specified via the keyboard, and forwards them to the core operating system for execution. This practically means that the user does not have to be a direct relationship with the core OS. Listed files represent monitor OS. The computer can not work if one of them is damaged or missing. If it does not use data compression DBLSPACE.??? group of files is not necessary.

COMMAND.COM file called the command processor and next to these tasks contains over 30 short of the necessary gadgets to perform everyday tasks. These gadgets are invited to perform by typing their names (KEYWORD) and possibly supplement and represent commands and orders the OS. The commands are executed immediately, and orders delayed because they seek more answers to queries. How are constantly working memory are said to be INTERNAL.

Q.1 (b)  Compare 8086, 80386 and i7 processor on the basis of architectural features.

Sr. No




1. The instruction Queue is 6 byte long. It is a 32 bit microprocessor and it is logical extension of the 80236. 64 bit
2. In 8086 memory divides into two banks, up to 1,048,576 bytes It is highly pipelined architecture and much faster speed bus than 8086. 32/64 bit Address bus
3. The data bus of 8086 is 16-bit wide However, 80386 can support 8086 programming model & can also directly run the programs  written for 8086 in virtual mode if VM=1(in protected mode) 64 GB Physical Memory
4. It has BHE# signal on pin no. 34 & there is no SSO# signal. The chip of 80836 contains 132 pins. 64 bit register size
5. The output signal is used to select memory or I/O at M/IO# but if IO#/M low or logic ‘0’ it selects I/O devices and if IO#/M is high or logic ‘1’it selects memory. The 80386 using High-speed CHMOS III technology. 1366 pin architecture
6. It needs one machine cycle to R/W signal if it is at even location otherwise it needs two. It has a special hardware for task switching. It support 8086 + 80386 + SIMD


7. In 8086, all address & data Buses are multiplexed. The 80386 operate 33MHz clock frequency maximum. L1: 32KB instruction cache +32 KB data cache

L2: 256 KB for each core

L3: 8 MB shared by all four cores

8. It needs two IC 74343 for de-multiplexing AD0-AD19. It has separate address and data bus for time saving. Hyper Threading


9.   Transistor density and complexity further increases 2,75,000 18 Bytes instruction cache
10.   It has total 129 instructions 6 (16 bit) segment registers
11.   The 80386  contains protection mechanism paging which has instruction two support them

GDTR: 80 bits

IDTR: 80 bits

LDTR: 16 bits

TR: 16 bits

Selector: 16 bits

Limit: 32 bits

Base: 64 bits

12.   It operate in three modes

1. Smart Cache

2. Virtualization Technology

3. Turbo Boost Technology

13.   It has instruction Queue as well as pre fetch queue.  
14.   It contains all nine flags of 8086 but other flags named IOP,NT,RF,VM  
15.   GDTR: 48 bits

IDTR: 48 bits

LDTR: 16 bits

TR: 16 bits

Selector: 16 bits

Limit: 16 bits

Base: 32 bits


Q.2 (a) Draw and explain block diagram of 8259APIC.

Ans: The 8259A is designed to minimize the software and real time overhead in handling multilevel priority interrupts It has several modes permitting optimization for a variety of system requirements.


  1. Vcc: SUPPLY  +5V Supply
  2. GND: Ground
  3. CS#: CHIP SELECT A low on this pin enables RD and WR communication between the CPU and the 8259A INTA functions are independent of CS.
  4. WR#: WRITE A low on this pin when CS is low enables the 8259A to accept
    command words from the CPU.
  5. RD#: READ A low on this pin when CS is low enables the 8259A to release
    status onto the data bus for the CPU.
  6. D7-D0: BIDIRECTIONAL DATA BUS Control status and interrupt-vector
    information is transferred via this bus.
  7. CAS0 –CAS2: CASCADE LINES The CAS lines form a private 8259A bus to control a multiple 8259A structure These pins are outputs for a master 8259A and inputs for a slave 8259A
  8. SP#/EN#:SLAVE PROGRAM ENABLE BUFFER This is a dual function pin
    When in the Buffered Mode it can be used as an output to control
    buffer transceivers (EN) When not in the buffered mode it is used as
    an input to designate a master (SP=1) or slave (SP=0).
  9. INT: INTERRUPT This pin goes high whenever a valid interrupt request is
    asserted It is used to interrupt the CPU thus it is connected to the
    CPU’s interrupt pin.
  10. IR0 –IR7: NTERRUPT REQUESTS Asynchronous inputs An interrupt request
    is executed by raising an IR input (low to high) and holding it high until
    it is acknowledged (Edge Triggered Mode) or just by a high level on an
    IR input (Level Triggered Mode).
  11. INTA#: INTERRUPT ACKNOWLEDGE This pin is used to enable 8259A
    interrupt-vector data onto the data bus by a sequence of interrupt
    acknowledge pulses issued by the CPU.
  12. A0: AO ADDRESS LINE This pin acts in conjunction with the CS WR and RD pins It is used by the 8259A to decipher various Command Words the CPU writes and status the CPU wishes to read It is typically connected to the CPU A0 address line (A1 for 8086 8088).

Q.2 (b) Write the initialization instructions of 8259A PIC, to meet the following specifications :
(i) Interrupt type 32.

(ii) Edge Triggered, single and ICW4 needed, interval of 8.

(iii) Mask IR1 & IR3 interrupts.


(i) Interrupt type 32 : On the PC, the BIOS (and thus also DOS) traditionally maps the master 8259 interrupt requests (IRQ0-IRQ7) to interrupt vector offset 8 (INT08-INT0F) and the slave 8259 (in PC/AT and later) interrupt requests (IRQ8-IRQ15) to interrupt vector offset 112 (INT70-INT77). This was done despite the first 32 (INT00-INT1F) interrupt vectors being reserved by the processor for internal exceptions (this was ignored for the design of the PC for some reason). Because of the reserved vectors for exceptions most other operating systems map (at least the master) 8259 IRQs (if used on a platform) to another interrupt vector base offset.

(ii) Edge Triggered, single and ICW4 needed, interval of 8:

SFNM: SFNM=1 the special fully nested mode is programmed

BUF: If BUF=1 the buffered mode is programmed In buffered mode SP#/EN# becomes an enable output and the master/slave determination is by M/S

M/S: If buffered mode is selected M/S=1 means the 8259A is programmed to be a master, M/S=0 means the 8259A is programmed to be a slave If BUF =0, M/S has no function

AEOI: If AEOI=1 the automatic end of interrupt mode is programmed.

Microprocessor mode: mPM=0 sets the 8259A for MCS-80, 85 system operation, mPM =1 sets the 8259A for 8086 system operation.

(iii) Mask IR1 & IR3 interrupts: Each Interrupt Request input can bem masked individually by the Interrupt Mask Register (IMR) programmed through OCW1 Each bit in the IMR masks one interrupt channel if it is set (1) Bit 0 masks IR0 Bit 1 masks IR1 and so forth Masking an IR channel does not affect the other channels operation

Q. 3 (a) Draw and explain I/O of BSR mode of 8255 with appropriate
control word formats.


BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 (if D0=1 then SET, D0=0 then RESET) of the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as given in table.

BSR Mode : CWR Format

D3 D2 D1 Selected bits of port C
0 0 0 D0
0 0 1 D1
0 1 0 D2
0 1 1 D3
1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

 Fig 1.9

Q.3 (b) Draw and discuss internal block diagram of 8251 USART.


The functional block diagram of 825 1A consists five sections. They are:
  1. Read/Write control logic
  2. Transmitter
  3. Receiver
  4. Data bus buffer
  5. Modem control.
The functional block diagram is shown in fig:


1. Read/Write control logic:The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register. It monitors the data flow. This section has three registers and they are control register, status register and data buffer. The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers. When C/D(low) is high, the control register is selected for writing control word or reading status word. When C/D(low) is low, the data buffer is selected for read/write operation. When the reset is high, it forces 8251A into the idle mode. The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

2. Transmitter section: The transmitter section accepts parallel data from CPU and converts them into serial data. The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits. When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. If buffer register is empty, then TxRDY is goes to high. If output register is empty then TxEMPTY goes to high. The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. The clock frequency can be 1,16 or 64 times the baud rate.

3. Receiver Section:The receiver section accepts serial data and convert them into parallel data. The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register. The CPU reads the parallel data from the buffer register.When the input register loads a parallel data to buffer register, the RxRDY line goes high. The clock signal RxC (low) controls the rate at which bits are received by the USART. During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

4. Data bus buffer: Data bus buffer is used to communicate with the system data bus. The data bus is D0-D7.

5. MODEM Control: The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

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