Q.3 (b) Define Resolution and Offset error terms of ADC.
|00||8-digit display with left entry|
|01||16-digit display with left entry|
|10||8-digit display with right entry|
|11||16-digit display with right entry|
Keyboard Interface of 8279 is as follows
|000||Encoded keyboard with 2-key lockout|
|001||Decoded keyboard with 2-key lockout|
|010||Encoded keyboard with N-key rollover|
|011||Decoded keyboard with N-key rollover|
|100||Encoded sensor matrix|
|101||Decoded sensor matrix|
|110||Strobed keyboard, encoded display scan|
|111||Strobed keyboard, decoded display scan|
Q.4 (c) Explain with neat diagram sequence of DMA operation.
Direct Memory Access:
- For devices that transfer large amount of data (such as disk controllers ), it is wasteful to tie up the CPU transferring data in and out of registers 8 bit at a time.
- Instead this work can be off loaded to a special processor, known as the Direct Memory Access, DMA and Controller.
- The host issues a command to the DMA controller, indicating the location where the data is located, the location where the data is to be transferred to, and the number of bytes of data to transfer. The DMA controller handles the data transfer, and then interrupts the CPU when the transfer is complete.
- A simple DMA controller is a standard component in modern PCs, and many bus mastering I/O cards contain their own DMA hardware.
- Handshaking between DMA controllers and their devices is accomplished through two wires called the DMA request and DMA acknowledge wires.
- While the DMA transfer is going on the CPU does not have access to the PCI bus (including main memory), but it does have access to its internal registers and primary and secondary caches.
- DMA can be done in terms of either physical addresses or virtual addresses that are mapped to physical addresses. The latter approach is known as Direct Virtual Memory Access, DVMA, and allows direct data transfer from one memory-mapped device to another without using the main memory chips.
- Direct DMA access by user processes can speed up operations, but is generally forbidden by modern systems for security and protection reasons. (I.e. DMA is a kernel-mode operation.)
- Figure illustrates the DMA process.
8087 math co processor can be connected with CPU only in maximum mode, i.e when MN/MX# pin is 0. In maximum mode, all control signals are derived using a bus controller. Multiplexed address data bus lines are connected directly from the 8086 to 8087. The status lines and the queue status lines connected directly from 8086 to 8087. The QS0 and QS1 lines may be directly connected to corresponding pins in case of 8086 based systems. The Request/Grant signal RQ#/GT0# of 8087 is connected to RQ#/GT1# of 8086.The clock pin of 8087 connected with CPU 8086 clock input. The interrupt output of 8087 is routed to 8086 via a programmable interrupt controller 8259.The pins AD0-AD15, BHE#/S7, RESET, A19/S6-A16/S3 are connected to corresponding pins of 8086. BUSY# signal 8087 is connected to TEST pin of 8086. Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition. A WAIT instruction is passed to keep looking at its TEST pin s, until it finds pin Low to indicates that the 8087 has completed the computation. SYNCHRONIZATION must be established between the processor and co-processor in two situations.
a) The execution of an ESC instruction that require the participation of the processor must not be initiated if the processor has not completed the execution of the previous instruction.
b) When a processor instruction accesses a memory location that is an operand of a previous co-processor instruction. In this case CPU must synchronize with processor to ensure that it has completed its instruction. Processor WAIT instruction is provided.
Figure shows the read cycle timing diagram. The read cycle begins in T1 with the enabling of the address latch enable (ALE) signal and also M/IO# signal. During the -ve going edge of this signal, the valid address is presented on the local bus. The BHE# and A0 signals address low, high or both bytes. From Tl to T4, the M/IO# signal indicates a memory or I/O operation. At T2 the address is removed from the local bus and is sent to the output. The bus is then enabled. The read (RD#) control signal is also activated in T2 .The read (RD#) signal causes the addressed device to enable its data bus drivers. After RD# goes negative, the valid data is available on the data bus. The addressed device will drive the READY line high, when the processor returns the read signal to high level, the addressed device will again enables its bus drivers.