3. Microprocessor and Interfacing Techniques SE Computer Engineering April/May 2014

Q.6 (a) With the help of neat diagram explain minimum mode configuration of 8086.

ANS: The minimum mode is selected by using logic 1 to the MN / MX# input pin. This is a single microprocessor configuration i.e. suppose we want to use single microprocessor like 80386 then we should use minimum mode.


HOLD: Hold is used to accept request from DMA controller it is input signal.

HLDA: It is nothing but the acknowledgment to the DMA if microprocessor is ready to accept the request from DMA then it generates HLDA signal, It is the output signals.

WR#: it is use to control the write operations.

M/IO#: When this signal is 1 then memory is selected for read and write operations. When this signal is 0 then I/O devices are selected for read and write operations.

DT/R#: When this signal is 1 then data transmission is selected i.e. data is transmitted from processor to external devices.When this signal is 0 then data receiver is selected i.e. data is received from external devices to processor.

DEN#: The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage.

ALE: Address Latch Enable means out of 16 AD0-AD15 multiplexed line the address bus is in used.

INTA#: Interrupt Acknowledgement INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.

Q.6 (b) Draw and explain format of control and status word of 8087 NDP.


Q.6 (b) Explain the following 8087 instructions with one example each :
(ii) FLDZ
(iii) FADD


(i) FSQRT: FSQRT instruction is use to calculate the square root of a number.

; Compute Z := sqrt(x**2 + y**2);

                fld     x       ;Load X.
                fld     st(0)   ;Duplicate X on TOS.
                fmul            ;Compute X**2.

                fld     y       ;Load Y.
                fld     st(0)   ;Duplicate Y on TOS.
                fmul            ;Compute Y**2.

                fadd            ;Compute X**2 + Y**2.
                fsqrt           ;Compute sqrt(x**2 + y**2).
                fst     Z       ;Store away result in Z.

(ii) FLDZ: This instruction decrements the TOP register pointer in the Status Word and loads the value of +0.0 into the new TOP data register.

Syntax:    fldz  (no operand)

Exception flags: Stack Fault, Invalid operation

(iii) FADD: Adds the destination and source operands and stores the sum in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or double word integer format.

EX: FADD ST(1),ST(2) ;this instruction add the second memory location with first memory location and the result is store in first memory location.

Q.7 (a) Explain the features of 82801 IJR I/O Controller Hub.


  1. I/O Controller hub used to manage communication between CPU and Motherboard.
  2. It support Advanced Configuration and Power Interface.
  3. It is integrated with IDE support.
  4. It support 24 interrupt sources. It support 33MHz PCI operation.

Q.7 (b) Draw and explain block diagram of X58 Chipset.


Intel Quick Path Interconnect (QPI): Intel’s latest system interconnect design increases bandwidth and lowers latency. Supports the Intel Core i7-965 processor Extreme Edition at 6.4 and 4.8 GT/s and Intel Core i7-940 and i7-920 processors.
PCI Express 2.0 Interface: PCI Express 2.0 delivers up to 16GB/s bandwidth per port, providing leading edge graphics performance and flexibility with support for dual x16 and up to quad x8 graphic card configurations, or any combinations in between. The Intel X58 IOH provides an additional 4 lanes that can be used for graphics or I/O for a total of 36 PCI Express lanes.
Intel High Definition Audio: Integrated audio support enables premium digital surround sound and delivers advanced features such as multiple audio streams and jack re tasking.
Intel Matrix Storage Technology: With additional hard drives added, provides quicker access to digital photo, video and data files with RAID 0, 5, and 10, and greater data protection against a hard disk drive failure with RAID 1, 5, and 10. Support for external SATA (eSATA) enables the full SATA interface speed outside the chassis, up to 3 Gb/s.
Intel Rapid Recover Technology: Intel’s latest data protection technology provides a recovery point that can be used to quickly recover a system should a hard drive fail or if there is data corruption. The clone can also be mounted as a read only volume to allow a user to recover individual files.
Intel Turbo Memory: Intel’s innovative NAND cache designed to improve the responsiveness of applications, application load times, and system boot performance. Intel Turbo Memory, paired with the Intel X58 Express Chip set, also allows the user to easily control the applications or data in the cache using the new Intel Turbo Memory Dashboard interface, boosting performance further. Serial ATA (SATA) 3 Gb/s High speed storage interface supports faster transfer rate for improved data access with up to 6 SATA ports.
eSATA: SATA interface designed for use with external SATA devices. It provides a link for 3 Gb/s data speeds to eliminate bottlenecks found with current external storage solutions. SATA Port Disable Enables individual SATA ports to be enabled or disabled as needed. This feature provides added protection of data by preventing malicious removal or insertion of data through SATA ports. Especially targeted for eSATA ports. USB Port Disable Enables individual USB ports to be enabled or disabled as needed. This feature provides added protection of data by preventing malicious removal or insertion of data through USB ports.

Q.8 (a) Draw and explain block diagram of i5 motherboard.


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System Memory Support: System memory features include:
• One or two channels of unbuffered DDR3 memory with a maximum of two UDIMMs per channel.
• Single and dual channel memory organization modes.
• Data burst length of eight for all memory organization modes.
• Memory DDR3 data transfer rates of 1066 MT/s and 1333 MT/s.
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
Direct Media Interface (DMI):
• Four lanes in each direction.
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of 250 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
• Shares 100-MHz PCI Express reference clock.
• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.
Thermal Management Support:
• Digital Thermal Sensor
•Intel Adaptive Thermal Monitor
• On Demand Mode
• Memory Thermal Throttling
• External Thermal Sensor
• Render Thermal Throttling
• Fan Speed Control with DTS

Q.8 (b) Write a short note on Intel’s QPI Technology.

ANS:New Bitmap Image (2)

Quick Path Interconnect(QPI): This architecture generally includes memory controllers integrated into the microprocessors, which are connected together with a high speed, point to point interconnect. The new Intel Quick Path Interconnect provides high bandwidth and low latency, which deliver the interconnect performance needed to unleash the new micro architecture and deliver the Reliability, Availability, and Serviceability (RAS) features expected in enterprise applications. This new interconnect is one piece of a balanced platform approach to achieving superior performance. It is a key ingredient in keeping pace with the next generation of microprocessors.


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