3. Microprocessor and Interfacing Techniques SE Computer Engineering April/May 2014

Q.6 (a) With the help of neat diagram explain minimum mode configuration of 8086.

ANS: The minimum mode is selected by using logic 1 to the MN / MX# input pin. This is a single microprocessor configuration i.e. suppose we want to use single microprocessor like 80386 then we should use minimum mode.


HOLD: Hold is used to accept request from DMA controller it is input signal.

HLDA: It is nothing but the acknowledgment to the DMA if microprocessor is ready to accept the request from DMA then it generates HLDA signal, It is the output signals.

WR#: it is use to control the write operations.

M/IO#: When this signal is 1 then memory is selected for read and write operations. When this signal is 0 then I/O devices are selected for read and write operations.

DT/R#: When this signal is 1 then data transmission is selected i.e. data is transmitted from processor to external devices.When this signal is 0 then data receiver is selected i.e. data is received from external devices to processor.

DEN#: The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage.

ALE: Address Latch Enable means out of 16 AD0-AD15 multiplexed line the address bus is in used.

INTA#: Interrupt Acknowledgement INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.

Q.6 (b) Draw and explain format of control and status word of 8087 NDP.


Q.6 (b) Explain the following 8087 instructions with one example each :
(ii) FLDZ
(iii) FADD


(i) FSQRT: FSQRT instruction is use to calculate the square root of a number.

; Compute Z := sqrt(x**2 + y**2);

                fld     x       ;Load X.
                fld     st(0)   ;Duplicate X on TOS.
                fmul            ;Compute X**2.

                fld     y       ;Load Y.
                fld     st(0)   ;Duplicate Y on TOS.
                fmul            ;Compute Y**2.

                fadd            ;Compute X**2 + Y**2.
                fsqrt           ;Compute sqrt(x**2 + y**2).
                fst     Z       ;Store away result in Z.

(ii) FLDZ: This instruction decrements the TOP register pointer in the Status Word and loads the value of +0.0 into the new TOP data register.

Syntax:    fldz  (no operand)

Exception flags: Stack Fault, Invalid operation

(iii) FADD: Adds the destination and source operands and stores the sum in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or double word integer format.

EX: FADD ST(1),ST(2) ;this instruction add the second memory location with first memory location and the result is store in first memory location.

Q.7 (a) Explain the features of 82801 IJR I/O Controller Hub.


  1. I/O Controller hub used to manage communication between CPU and Motherboard.
  2. It support Advanced Configuration and Power Interface.
  3. It is integrated with IDE support.
  4. It support 24 interrupt sources. It support 33MHz PCI operation.

Q.7 (b) Draw and explain block diagram of X58 Chipset.


Intel Quick Path Interconnect (QPI): Intel’s latest system interconnect design increases bandwidth and lowers latency. Supports the Intel Core i7-965 processor Extreme Edition at 6.4 and 4.8 GT/s and Intel Core i7-940 and i7-920 processors.
PCI Express 2.0 Interface: PCI Express 2.0 delivers up to 16GB/s bandwidth per port, providing leading edge graphics performance and flexibility with support for dual x16 and up to quad x8 graphic card configurations, or any combinations in between. The Intel X58 IOH provides an additional 4 lanes that can be used for graphics or I/O for a total of 36 PCI Express lanes.
Intel High Definition Audio: Integrated audio support enables premium digital surround sound and delivers advanced features such as multiple audio streams and jack re tasking.
Intel Matrix Storage Technology: With additional hard drives added, provides quicker access to digital photo, video and data files with RAID 0, 5, and 10, and greater data protection against a hard disk drive failure with RAID 1, 5, and 10. Support for external SATA (eSATA) enables the full SATA interface speed outside the chassis, up to 3 Gb/s.
Intel Rapid Recover Technology: Intel’s latest data protection technology provides a recovery point that can be used to quickly recover a system should a hard drive fail or if there is data corruption. The clone can also be mounted as a read only volume to allow a user to recover individual files.
Intel Turbo Memory: Intel’s innovative NAND cache designed to improve the responsiveness of applications, application load times, and system boot performance. Intel Turbo Memory, paired with the Intel X58 Express Chip set, also allows the user to easily control the applications or data in the cache using the new Intel Turbo Memory Dashboard interface, boosting performance further. Serial ATA (SATA) 3 Gb/s High speed storage interface supports faster transfer rate for improved data access with up to 6 SATA ports.
eSATA: SATA interface designed for use with external SATA devices. It provides a link for 3 Gb/s data speeds to eliminate bottlenecks found with current external storage solutions. SATA Port Disable Enables individual SATA ports to be enabled or disabled as needed. This feature provides added protection of data by preventing malicious removal or insertion of data through SATA ports. Especially targeted for eSATA ports. USB Port Disable Enables individual USB ports to be enabled or disabled as needed. This feature provides added protection of data by preventing malicious removal or insertion of data through USB ports.

Q.8 (a) Draw and explain block diagram of i5 motherboard.


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System Memory Support: System memory features include:
• One or two channels of unbuffered DDR3 memory with a maximum of two UDIMMs per channel.
• Single and dual channel memory organization modes.
• Data burst length of eight for all memory organization modes.
• Memory DDR3 data transfer rates of 1066 MT/s and 1333 MT/s.
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
Direct Media Interface (DMI):
• Four lanes in each direction.
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of 250 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
• Shares 100-MHz PCI Express reference clock.
• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.
Thermal Management Support:
• Digital Thermal Sensor
•Intel Adaptive Thermal Monitor
• On Demand Mode
• Memory Thermal Throttling
• External Thermal Sensor
• Render Thermal Throttling
• Fan Speed Control with DTS

Q.8 (b) Write a short note on Intel’s QPI Technology.

ANS:New Bitmap Image (2)

Quick Path Interconnect(QPI): This architecture generally includes memory controllers integrated into the microprocessors, which are connected together with a high speed, point to point interconnect. The new Intel Quick Path Interconnect provides high bandwidth and low latency, which deliver the interconnect performance needed to unleash the new micro architecture and deliver the Reliability, Availability, and Serviceability (RAS) features expected in enterprise applications. This new interconnect is one piece of a balanced platform approach to achieving superior performance. It is a key ingredient in keeping pace with the next generation of microprocessors.


2. Microprocessor and Interfacing Techniques SE Computer Engineering April/May 2014

Q.3 (b) Define Resolution and Offset error terms of ADC.

Resolution: The number of bits in the output code of the ADC, this term has no real bearing on the performance of the ADC except that all performance parameters are measured against the theoretical best ADC of equal resolution.
Offset Error (E0): The difference between the actual and ideal first transition voltages.
Q.4 (a) Design a control word format for square wave generator with 1ms period, the input frequency for 8253 is 1 MHz.
Square Wave Generator:
Mode 3 is used for square wave generator, the control word format is as follows.
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In this control word format
D0= Binary counter so D0=0
D1, D2, D3 bits are used to define mode so for square wave generator we require mode 3, so mode 3=0(M2),1(M1),1(M2).
D4 & D5 are use for Read/load least significant byte first, then most significant byte. So D4=1 & D5=1.
D6 & D7 are use to select the counter so for square wave generator we require counter 0, so D6=0 & D7=0.
So the final control word= 00110110
i.e 36H is the control word.
MOV AX, 36H (Control word is move into AX register).
Q.4 (b) Draw and explain the following 8279 commands :
(i) Keyboard/Display mode set command
(ii) Read FIFO/Sensor RAM command.
ANS: (i) Keyboard/Display mode set command:
All the command words or status words are written and read with A0=1
 D5=0, D6=0 & D7=0 configuration is used for mode set.
Now D3=D & D4=D is used to set display configuration as follows.
008-digit display with left entry
0116-digit display with left entry
108-digit display with right entry
1116-digit display with right entry

Keyboard Interface of 8279 is as follows

000Encoded keyboard with 2-key lockout
001Decoded keyboard with 2-key lockout
010Encoded keyboard with N-key rollover
011Decoded keyboard with N-key rollover
100Encoded sensor matrix
101Decoded sensor matrix
110Strobed keyboard, encoded display scan
111Strobed keyboard, decoded display scan

Q.4 (c) Explain with neat diagram sequence of DMA operation.

Direct Memory Access:

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  1. For devices that transfer large amount of data (such as disk controllers ), it is wasteful to tie up the CPU transferring data in and out of registers 8 bit at a time.
  2. Instead this work can be off loaded to a special processor, known as the Direct Memory Access, DMA and Controller.
  3. The host issues a command to the DMA controller, indicating the location where the data is located, the location where the data is to be transferred to, and the number of bytes of data to transfer. The DMA controller handles the data transfer, and then interrupts the CPU when the transfer is complete.
  4. A simple DMA controller is a standard component in modern PCs, and many bus mastering I/O cards contain their own DMA hardware.
  5. Handshaking between DMA controllers and their devices is accomplished through two wires called the DMA request and DMA acknowledge wires.
  6. While the DMA transfer is going on the CPU does not have access to the PCI bus (including main memory), but it does have access to its internal registers and primary and secondary caches.
  7. DMA can be done in terms of either physical addresses or virtual addresses that are mapped to physical addresses. The latter approach is known as Direct Virtual Memory Access, DVMA, and allows direct data transfer from one memory-mapped device to another without using the main memory chips.
  8. Direct DMA access by user processes can speed up operations, but is generally forbidden by modern systems for security and protection reasons. (I.e. DMA is a kernel-mode operation.)
  9. Figure illustrates the DMA process.
Q.5 (a) Draw and discuss the interface between 8086 and 8087.

8087 math co processor can be connected with CPU only in maximum mode, i.e when MN/MX# pin is 0. In maximum mode, all control signals are derived using a bus controller. Multiplexed address data bus lines are connected directly from the 8086 to 8087. The status lines and the queue status lines connected directly from 8086 to 8087. The QS0 and QS1 lines may be directly connected to corresponding pins in case of 8086 based systems. The Request/Grant signal RQ#/GT0# of 8087 is connected to RQ#/GT1# of 8086.The clock pin of 8087 connected with CPU 8086 clock input. The interrupt output of 8087 is routed to 8086 via a programmable interrupt controller 8259.The pins AD0-AD15, BHE#/S7, RESET, A19/S6-A16/S3 are connected  to corresponding pins of 8086. BUSY# signal 8087 is connected to TEST pin of 8086. Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition. A WAIT instruction is passed to keep looking at its TEST pin s, until it finds pin Low to indicates that the 8087 has completed the computation. SYNCHRONIZATION must be established between the processor and co-processor in two situations.

a) The execution of an ESC instruction that require the participation of the processor must not be initiated if the processor has not completed the execution of the previous instruction.

b) When a processor instruction accesses a memory location that is an operand of a previous co-processor instruction. In this case CPU must synchronize with processor to ensure that it has completed its instruction. Processor WAIT instruction is provided.

Q.5 (b) With proper timing diagram explain Read cycle in minimum mode of 8086 microprocessor.

Figure shows the read cycle timing diagram. The read cycle begins in T1 with the enabling of the address latch enable (ALE) signal and also M/IO# signal. During the -ve going edge of this signal, the valid address is presented on the local bus. The BHE# and A0 signals address low, high or both bytes. From Tl to T4, the M/IO# signal indicates a memory or I/O operation. At T2 the address is removed from the local bus and is sent to the output. The bus is then enabled. The read (RD#) control signal is also activated in T2 .The read (RD#) signal causes the addressed device to enable its data bus drivers. After RD# goes negative, the valid data is available on the data bus. The addressed device will drive the READY line high, when the processor returns the read signal to high level, the addressed device will again enables its bus drivers.




1. Microprocessor and Interfacing Techniques SE Computer Engineering April/May 2014

Q.1 (a) What are the different component of MS-DOS? Explain DOS loading with the help of neat diagram


MS-DOS is created using following three files.




These files are created for special purpose like  creating, booting and coordinating with devices for input, output  and saving internal commands of DOS in memory.In other words these are program files which are created which creating DOS.

IO.SYS: These two files are hidden files. These are system files and are present on every disc. At the time of booting both of these Files are automatically get saved in Temporary Memory. IO.sys stores the standard operation related to input and output devices. And MSDOS.sys file stores command that contact with operating system.

COMMAND.COM :This is a command interpreter file in MS-DOS which is a group of IO.sys, MSDOS.sys and COMMAND.COM. At the time of booting of computer, all these three files are automatically saved in the memory. COMMAND.COM file contains all the definitions of Internal command and programs of these commands. This file is mainly responsible for executing command which are typed by user in command prompt.

AUTOEXE.BAT: After booting Operating System it looks for AUTOEXE.BAT file in the disc and executes it. This process is repeated when computer is switched on. It is a batch file which contains MS-DOS command like a program file and it automatically executes the command written in it. Therefore it is named AUTOEXE.BAT which means self executable batch file. BIOS is a set of basic instructions and drivers for the monitor, keyboard, printer, I / O ports and other devices in the PC configurations. The task of the BIOS is to mediate between the demands of the remaining parts of the OS and all of these devices. BIOS each OS translates the request into a series of instructions that the microprocessor controlled devices. Many manufacturers expand content BIOS variety of additional features, such as antivirus software, since current technology allows, but for correct operation must not disturb the base that must be the same as the IBM BIOS. When the BIOS enables the microprocessor to make contact with the disk (partition) on which the operating system, the command for copying files to the following picture.

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MSDOS.SYS and IO.SYS form the CORE of the operating system. Group DBLSPACE.??? used when the data is compressed on disk. COMMAND.COM is INTERPRETER (simultaneous interpreter) command, which the user specified via the keyboard, and forwards them to the core operating system for execution. This practically means that the user does not have to be a direct relationship with the core OS. Listed files represent monitor OS. The computer can not work if one of them is damaged or missing. If it does not use data compression DBLSPACE.??? group of files is not necessary.

COMMAND.COM file called the command processor and next to these tasks contains over 30 short of the necessary gadgets to perform everyday tasks. These gadgets are invited to perform by typing their names (KEYWORD) and possibly supplement and represent commands and orders the OS. The commands are executed immediately, and orders delayed because they seek more answers to queries. How are constantly working memory are said to be INTERNAL.

Q.1 (b)  Compare 8086, 80386 and i7 processor on the basis of architectural features.

Sr. No




1.The instruction Queue is 6 byte long.It is a 32 bit microprocessor and it is logical extension of the 80236.64 bit
2.In 8086 memory divides into two banks, up to 1,048,576 bytesIt is highly pipelined architecture and much faster speed bus than 8086.32/64 bit Address bus
3.The data bus of 8086 is 16-bit wideHowever, 80386 can support 8086 programming model & can also directly run the programs  written for 8086 in virtual mode if VM=1(in protected mode)64 GB Physical Memory
4.It has BHE# signal on pin no. 34 & there is no SSO# signal.The chip of 80836 contains 132 pins.64 bit register size
5.The output signal is used to select memory or I/O at M/IO# but if IO#/M low or logic ‘0’ it selects I/O devices and if IO#/M is high or logic ‘1’it selects memory.The 80386 using High-speed CHMOS III technology.1366 pin architecture
6.It needs one machine cycle to R/W signal if it is at even location otherwise it needs two.It has a special hardware for task switching.It support 8086 + 80386 + SIMD


7.In 8086, all address & data Buses are multiplexed.The 80386 operate 33MHz clock frequency maximum.L1: 32KB instruction cache +32 KB data cache

L2: 256 KB for each core

L3: 8 MB shared by all four cores

8.It needs two IC 74343 for de-multiplexing AD0-AD19.It has separate address and data bus for time saving.Hyper Threading


9. Transistor density and complexity further increases 2,75,00018 Bytes instruction cache
10. It has total 129 instructions6 (16 bit) segment registers
11. The 80386  contains protection mechanism paging which has instruction two support them

GDTR: 80 bits

IDTR: 80 bits

LDTR: 16 bits

TR: 16 bits

Selector: 16 bits

Limit: 32 bits

Base: 64 bits

12. It operate in three modes

1. Smart Cache

2. Virtualization Technology

3. Turbo Boost Technology

13. It has instruction Queue as well as pre fetch queue. 
14. It contains all nine flags of 8086 but other flags named IOP,NT,RF,VM 
15. GDTR: 48 bits

IDTR: 48 bits

LDTR: 16 bits

TR: 16 bits

Selector: 16 bits

Limit: 16 bits

Base: 32 bits


Q.2 (a) Draw and explain block diagram of 8259APIC.

Ans: The 8259A is designed to minimize the software and real time overhead in handling multilevel priority interrupts It has several modes permitting optimization for a variety of system requirements.


  1. Vcc: SUPPLY  +5V Supply
  2. GND: Ground
  3. CS#: CHIP SELECT A low on this pin enables RD and WR communication between the CPU and the 8259A INTA functions are independent of CS.
  4. WR#: WRITE A low on this pin when CS is low enables the 8259A to accept
    command words from the CPU.
  5. RD#: READ A low on this pin when CS is low enables the 8259A to release
    status onto the data bus for the CPU.
  6. D7-D0: BIDIRECTIONAL DATA BUS Control status and interrupt-vector
    information is transferred via this bus.
  7. CAS0 –CAS2: CASCADE LINES The CAS lines form a private 8259A bus to control a multiple 8259A structure These pins are outputs for a master 8259A and inputs for a slave 8259A
  8. SP#/EN#:SLAVE PROGRAM ENABLE BUFFER This is a dual function pin
    When in the Buffered Mode it can be used as an output to control
    buffer transceivers (EN) When not in the buffered mode it is used as
    an input to designate a master (SP=1) or slave (SP=0).
  9. INT: INTERRUPT This pin goes high whenever a valid interrupt request is
    asserted It is used to interrupt the CPU thus it is connected to the
    CPU’s interrupt pin.
  10. IR0 –IR7: NTERRUPT REQUESTS Asynchronous inputs An interrupt request
    is executed by raising an IR input (low to high) and holding it high until
    it is acknowledged (Edge Triggered Mode) or just by a high level on an
    IR input (Level Triggered Mode).
  11. INTA#: INTERRUPT ACKNOWLEDGE This pin is used to enable 8259A
    interrupt-vector data onto the data bus by a sequence of interrupt
    acknowledge pulses issued by the CPU.
  12. A0: AO ADDRESS LINE This pin acts in conjunction with the CS WR and RD pins It is used by the 8259A to decipher various Command Words the CPU writes and status the CPU wishes to read It is typically connected to the CPU A0 address line (A1 for 8086 8088).

Q.2 (b) Write the initialization instructions of 8259A PIC, to meet the following specifications :
(i) Interrupt type 32.

(ii) Edge Triggered, single and ICW4 needed, interval of 8.

(iii) Mask IR1 & IR3 interrupts.


(i) Interrupt type 32 : On the PC, the BIOS (and thus also DOS) traditionally maps the master 8259 interrupt requests (IRQ0-IRQ7) to interrupt vector offset 8 (INT08-INT0F) and the slave 8259 (in PC/AT and later) interrupt requests (IRQ8-IRQ15) to interrupt vector offset 112 (INT70-INT77). This was done despite the first 32 (INT00-INT1F) interrupt vectors being reserved by the processor for internal exceptions (this was ignored for the design of the PC for some reason). Because of the reserved vectors for exceptions most other operating systems map (at least the master) 8259 IRQs (if used on a platform) to another interrupt vector base offset.

(ii) Edge Triggered, single and ICW4 needed, interval of 8:

SFNM: SFNM=1 the special fully nested mode is programmed

BUF: If BUF=1 the buffered mode is programmed In buffered mode SP#/EN# becomes an enable output and the master/slave determination is by M/S

M/S: If buffered mode is selected M/S=1 means the 8259A is programmed to be a master, M/S=0 means the 8259A is programmed to be a slave If BUF =0, M/S has no function

AEOI: If AEOI=1 the automatic end of interrupt mode is programmed.

Microprocessor mode: mPM=0 sets the 8259A for MCS-80, 85 system operation, mPM =1 sets the 8259A for 8086 system operation.

(iii) Mask IR1 & IR3 interrupts: Each Interrupt Request input can bem masked individually by the Interrupt Mask Register (IMR) programmed through OCW1 Each bit in the IMR masks one interrupt channel if it is set (1) Bit 0 masks IR0 Bit 1 masks IR1 and so forth Masking an IR channel does not affect the other channels operation

Q. 3 (a) Draw and explain I/O of BSR mode of 8255 with appropriate
control word formats.


BSR Mode: In this mode any of the 8-bits of port C can be set or reset depending on D0 (if D0=1 then SET, D0=0 then RESET) of the control word. The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR as given in table.

BSR Mode : CWR Format

D3D2D1Selected bits of port C

 Fig 1.9

Q.3 (b) Draw and discuss internal block diagram of 8251 USART.


The functional block diagram of 825 1A consists five sections. They are:
  1. Read/Write control logic
  2. Transmitter
  3. Receiver
  4. Data bus buffer
  5. Modem control.
The functional block diagram is shown in fig:


1. Read/Write control logic:The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register. It monitors the data flow. This section has three registers and they are control register, status register and data buffer. The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers. When C/D(low) is high, the control register is selected for writing control word or reading status word. When C/D(low) is low, the data buffer is selected for read/write operation. When the reset is high, it forces 8251A into the idle mode. The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

2. Transmitter section: The transmitter section accepts parallel data from CPU and converts them into serial data. The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits. When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register. If buffer register is empty, then TxRDY is goes to high. If output register is empty then TxEMPTY goes to high. The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART. The clock frequency can be 1,16 or 64 times the baud rate.

3. Receiver Section:The receiver section accepts serial data and convert them into parallel data. The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again. If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register. The CPU reads the parallel data from the buffer register.When the input register loads a parallel data to buffer register, the RxRDY line goes high. The clock signal RxC (low) controls the rate at which bits are received by the USART. During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission. During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

4. Data bus buffer: Data bus buffer is used to communicate with the system data bus. The data bus is D0-D7.

5. MODEM Control: The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

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