For any android device flashing, software upgrade and other recovery we required recovery mode now in this tutorial we study steps to enter into recovery mode initially the recovery mode is not activated then after pressing power button the menu is displayed as follows.
Step1: Open the setting from your device like as shown in this screenshot.
Step2: Click on about phone like show in screenshot currently there is no option of developer mode.
Step3: Then 6 times click on the build number as show in screenshot, then the developer option gets visible.
Step4: Click on developer option after that choose advance reboot option and enable it.
Step5: Now exit from all menus and press power off button then choose recovery option from it then click on OK now at next start-up your recovery mode gets enable now you can flash, update your device.
AdSense is one of the most famous method to earn revenue from quality web contains. But one problem is that AdSense doesn’t give approval easily it is hard task. So after rejection from AdSense the blogger needed alternatives so the following are the most famous alternatives for AdSense.
1. Infolinks.com: infolink is not a scam it is really effective method of earning from web contents. If you hove quality contain add traffic from all over the world then you can definitely earn mony from it. It is effective if your traffic comes from US and western countries. So the blogger whose more traffic from these countries then he can earn more using infolink. The registration process is easy you can click on above link and register then if you are using CMS like WordPress blogger then you can install the plugin and easily add the advertisement code. After couple of days you receive positive response from them that’s it, For registrations click here..
2. Media.net: Media.net is also a effective medium to earn more from blog but it also has hard policy of approval. Media.net is the combined work of Yahoo and Bing. Once registration is completed their representative take review of your content and give reply. To register click here…
In YouTube the CPC is the important part of earnings, so if CPC is low then you earn less amount of revenue, so in this tutorial I explain you how to increase YouTube. Generally if your video views are 1000 and clicks are 30 and CPC is 0.02 then you can earn $0.60, in same situation suppose CPC is 0.05 then you can earn $1.5 so CPC plays important role in YouTube earning. Following are the steps to increase CPC.
Step1: Suppose CPC is 0.02 then open your video don’t login into your account after some time the add is display on your video so, click on that add.
Step2: If you using Firefox then open private window and login to AdSense account. In upper menu one tab is there allow and block add click on it.
Step3: Clicks on advertiser’s URL then paste the URL of advertisements. Then click on block URL.
Step4: click on content host and paste only website address and block it also.
Step5: after some time check the CPC if it is still 0.02 after some post clicks then repeat steps 1 to 4 again after some time your CPC gets definitely increased.
In some case though the CPC is low but the CPM is high, the meaning of CPM is cost per million impression. So CPC is not only one factor to increase earning but you should consider CPM also for that before blocking some URL consider the popularity of that site also for higher CPM that’s it Thanks.
Some YUPHORIA devices gives problem after updating to 12.1 so you need to re flash the device to previous version 12.0 below are the steps for flashing YUPHORIA device.
1. Before following below steps please take the backup of your device data as your entire phone data will be wiped. This process may take some 40-45 mins for full boot up.
2. Make sure that your phone has enough battery power for the installation process (and the download too, if set to manual). The update process will work best if your phone has at least half of its battery life available, or if you plug it into an outlet during the installation process.
3. Follow the CM12S OTA flashing process for lollipop update with incremental OTA update mentioned below to resolve the issuewith the new updates:
Q.6 (a) With the help of neat diagram explain minimum mode configuration of 8086.
ANS: The minimum mode is selected by using logic 1 to the MN / MX# input pin. This is a single microprocessor configuration i.e. suppose we want to use single microprocessor like 80386 then we should use minimum mode.
HOLD: Hold is used to accept request from DMA controller it is input signal.
HLDA: It is nothing but the acknowledgment to the DMA if microprocessor is ready to accept the request from DMA then it generates HLDA signal, It is the output signals.
WR#: it is use to control the write operations.
M/IO#: When this signal is 1 then memory is selected for read and write operations. When this signal is 0 then I/O devices are selected for read and write operations.
DT/R#: When this signal is 1 then data transmission is selected i.e. data is transmitted from processor to external devices.When this signal is 0 then data receiver is selected i.e. data is received from external devices to processor.
DEN#: The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage.
ALE: Address Latch Enable means out of 16 AD0-AD15 multiplexed line the address bus is in used.
INTA#: Interrupt Acknowledgement INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.
Q.6 (b) Draw and explain format of control and status word of 8087 NDP.
Q.6 (b) Explain the following 8087 instructions with one example each : (i) FSQRT (ii) FLDZ (iii) FADD
(i) FSQRT: FSQRT instruction is use to calculate the square root of a number.
; Compute Z := sqrt(x**2 + y**2);
fld x ;Load X.
fld st(0) ;Duplicate X on TOS.
fmul ;Compute X**2.
fld y ;Load Y.
fld st(0) ;Duplicate Y on TOS.
fmul ;Compute Y**2.
fadd ;Compute X**2 + Y**2.
fsqrt ;Compute sqrt(x**2 + y**2).
fst Z ;Store away result in Z.
(ii) FLDZ: This instruction decrements the TOP register pointer in the Status Word and loads the value of +0.0 into the new TOP data register.
Syntax: fldz (no operand)
Exception flags: Stack Fault, Invalid operation
(iii) FADD:Adds the destination and source operands and stores the sum in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or double word integer format.
EX: FADD ST(1),ST(2) ;this instruction add the second memory location with first memory location and the result is store in first memory location.
Q.7 (a) Explain the features of 82801 IJR I/O Controller Hub.
I/O Controller hub used to manage communication between CPU and Motherboard.
It support Advanced Configuration and Power Interface.
It is integrated with IDE support.
It support 24 interrupt sources. It support 33MHz PCI operation.
Q.7 (b) Draw and explain block diagram of X58 Chipset.
Intel Quick Path Interconnect (QPI): Intel’s latest system interconnect design increases bandwidth and lowers latency. Supports the Intel Core i7-965 processor Extreme Edition at 6.4 and 4.8 GT/s and Intel Core i7-940 and i7-920 processors.
PCI Express 2.0 Interface: PCI Express 2.0 delivers up to 16GB/s bandwidth per port, providing leading edge graphics performance and flexibility with support for dual x16 and up to quad x8 graphic card configurations, or any combinations in between. The Intel X58 IOH provides an additional 4 lanes that can be used for graphics or I/O for a total of 36 PCI Express lanes.
Intel High Definition Audio: Integrated audio support enables premium digital surround sound and delivers advanced features such as multiple audio streams and jack re tasking.
Intel Matrix Storage Technology: With additional hard drives added, provides quicker access to digital photo, video and data files with RAID 0, 5, and 10, and greater data protection against a hard disk drive failure with RAID 1, 5, and 10. Support for external SATA (eSATA) enables the full SATA interface speed outside the chassis, up to 3 Gb/s.
Intel Rapid Recover Technology: Intel’s latest data protection technology provides a recovery point that can be used to quickly recover a system should a hard drive fail or if there is data corruption. The clone can also be mounted as a read only volume to allow a user to recover individual files.
Intel Turbo Memory: Intel’s innovative NAND cache designed to improve the responsiveness of applications, application load times, and system boot performance. Intel Turbo Memory, paired with the Intel X58 Express Chip set, also allows the user to easily control the applications or data in the cache using the new Intel Turbo Memory Dashboard interface, boosting performance further. Serial ATA (SATA) 3 Gb/s High speed storage interface supports faster transfer rate for improved data access with up to 6 SATA ports.
eSATA: SATA interface designed for use with external SATA devices. It provides a link for 3 Gb/s data speeds to eliminate bottlenecks found with current external storage solutions. SATA Port Disable Enables individual SATA ports to be enabled or disabled as needed. This feature provides added protection of data by preventing malicious removal or insertion of data through SATA ports. Especially targeted for eSATA ports. USB Port Disable Enables individual USB ports to be enabled or disabled as needed. This feature provides added protection of data by preventing malicious removal or insertion of data through USB ports.
Q.8 (a) Draw and explain block diagram of i5 motherboard.
System Memory Support: System memory features include:
• One or two channels of unbuffered DDR3 memory with a maximum of two UDIMMs per channel.
• Single and dual channel memory organization modes.
• Data burst length of eight for all memory organization modes.
• Memory DDR3 data transfer rates of 1066 MT/s and 1333 MT/s.
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
Direct Media Interface (DMI):
• Four lanes in each direction.
• 2.5 GT/s point-to-point DMI interface to PCH is supported.
• Raw bit-rate on the data pins of 2.5 GB/s, resulting in a real bandwidth per pair of 250 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 1 GB/s in each direction
simultaneously, for an aggregate of 2 GB/s when DMI x4.
• Shares 100-MHz PCI Express reference clock.
• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.
Thermal Management Support:
• Digital Thermal Sensor
•Intel Adaptive Thermal Monitor
• THERMTRIP and PROCHOT support
• On Demand Mode
• Memory Thermal Throttling
• External Thermal Sensor
• Render Thermal Throttling
• Fan Speed Control with DTS
Q.8 (b) Write a short note on Intel’s QPI Technology.
Quick Path Interconnect(QPI): This architecture generally includes memory controllers integrated into the microprocessors, which are connected together with a high speed, point to point interconnect. The new Intel Quick Path Interconnect provides high bandwidth and low latency, which deliver the interconnect performance needed to unleash the new micro architecture and deliver the Reliability, Availability, and Serviceability (RAS) features expected in enterprise applications. This new interconnect is one piece of a balanced platform approach to achieving superior performance. It is a key ingredient in keeping pace with the next generation of microprocessors.
Step 1: Create quality knowledge based stuff online for that you can choose either free platform like blogger.com, wordpress.com for creating quality blogs and technical writing or you can purchase domain and hosting from godaddy.com, bigrock.com and create your own blogging site.
Step 2: Make sure that your site must contain more than 16 quality posts. If you use free blogging sites like blogger and you are from india and china you should run it successfully more than 6 months because AdSense does not approve blogs which is less than 6 months old.
Step 3: Sign up for AdSense for that use your gmail account, enter the url on which you want to display adds after that enter the payee name as per the bank account. After registration click on My ads then create new add unit, after that click on get code, copy this code and past it on your webpages.
Step 4: Wait for a week for AdSense reply. If everything is fine you received acknowledgment from AdSense but in case of some requirements they assist you to fulfill this requirements. If AdSense rejected your application don’t worry made the changes which are suggested by their representative and reapply for AdSense.
Q.3 (b) Define Resolution and Offset error terms of ADC.
Resolution: The number of bits in the output code of the ADC, this term has no real bearing on the performance of the ADC except that all performance parameters are measured against the theoretical best ADC of equal resolution.
Offset Error (E0): The difference between the actual and ideal first transition voltages.
Q.4 (a) Design a control word format for square wave generator with 1ms period, the input frequency for 8253 is 1 MHz.
Square Wave Generator:
Mode 3 is used for square wave generator, the control word format is as follows.
In this control word format
D0= Binary counter so D0=0
D1, D2, D3 bits are used to define mode so for square wave generator we require mode 3, so mode 3=0(M2),1(M1),1(M2).
D4 & D5 are use for Read/load least significant byte first, then most significant byte. So D4=1 & D5=1.
D6 & D7 are use to select the counter so for square wave generator we require counter 0, so D6=0 & D7=0.
So the final control word= 00110110
i.e 36H is the control word.
MOV AX, 36H (Control word is move into AX register).
Q.4 (b) Draw and explain the following 8279 commands :
(i) Keyboard/Display mode set command
(ii) Read FIFO/Sensor RAM command.
ANS: (i) Keyboard/Display mode set command:
All the command words or status words are written and read with A0=1
D5=0, D6=0 & D7=0 configuration is used for mode set.
Now D3=D & D4=D is used to set display configuration as follows.
8-digit display with left entry
16-digit display with left entry
8-digit display with right entry
16-digit display with right entry
Keyboard Interface of 8279 is as follows
Encoded keyboard with 2-key lockout
Decoded keyboard with 2-key lockout
Encoded keyboard with N-key rollover
Decoded keyboard with N-key rollover
Encoded sensor matrix
Decoded sensor matrix
Strobed keyboard, encoded display scan
Strobed keyboard, decoded display scan
Q.4 (c) Explain with neat diagram sequence of DMA operation.
Direct Memory Access:
For devices that transfer large amount of data (such as disk controllers ), it is wasteful to tie up the CPU transferring data in and out of registers 8 bit at a time.
Instead this work can be off loaded to a special processor, known as the Direct Memory Access, DMA and Controller.
The host issues a command to the DMA controller, indicating the location where the data is located, the location where the data is to be transferred to, and the number of bytes of data to transfer. The DMA controller handles the data transfer, and then interrupts the CPU when the transfer is complete.
A simple DMA controller is a standard component in modern PCs, and many bus mastering I/O cards contain their own DMA hardware.
Handshaking between DMA controllers and their devices is accomplished through two wires called the DMA request and DMA acknowledge wires.
While the DMA transfer is going on the CPU does not have access to the PCI bus (including main memory), but it does have access to its internal registers and primary and secondary caches.
DMA can be done in terms of either physical addresses or virtual addresses that are mapped to physical addresses. The latter approach is known as Direct Virtual Memory Access, DVMA, and allows direct data transfer from one memory-mapped device to another without using the main memory chips.
Direct DMA access by user processes can speed up operations, but is generally forbidden by modern systems for security and protection reasons. (I.e. DMA is a kernel-mode operation.)
Figure illustrates the DMA process.
Q.5 (a) Draw and discuss the interface between 8086 and 8087.
8087 math co processor can be connected with CPU only in maximum mode, i.e when MN/MX# pin is 0. In maximum mode, all control signals are derived using a bus controller. Multiplexed address data bus lines are connected directly from the 8086 to 8087. The status lines and the queue status lines connected directly from 8086 to 8087. The QS0 and QS1 lines may be directly connected to corresponding pins in case of 8086 based systems. The Request/Grant signal RQ#/GT0# of 8087 is connected to RQ#/GT1# of 8086.The clock pin of 8087 connected with CPU 8086 clock input. The interrupt output of 8087 is routed to 8086 via a programmable interrupt controller 8259.The pins AD0-AD15, BHE#/S7, RESET, A19/S6-A16/S3 are connected to corresponding pins of 8086. BUSY# signal 8087 is connected to TEST pin of 8086. Interrupt output INT of the 8087 to NMI input of 8086. This intimates an error condition. A WAIT instruction is passed to keep looking at its TEST pin s, until it finds pin Low to indicates that the 8087 has completed the computation. SYNCHRONIZATION must be established between the processor and co-processor in two situations.
a) The execution of an ESC instruction that require the participation of the processor must not be initiated if the processor has not completed the execution of the previous instruction.
b) When a processor instruction accesses a memory location that is an operand of a previous co-processor instruction. In this case CPU must synchronize with processor to ensure that it has completed its instruction. Processor WAIT instruction is provided.
Q.5 (b) With proper timing diagram explain Read cycle in minimum mode of 8086 microprocessor.
Figure shows the read cycle timing diagram. The read cycle begins in T1 with the enabling of the address latch enable (ALE) signal and also M/IO# signal. During the -ve going edge of this signal, the valid address is presented on the local bus. The BHE# and A0 signals address low, high or both bytes. From Tl to T4, the M/IO# signal indicates a memory or I/O operation. At T2 the address is removed from the local bus and is sent to the output. The bus is then enabled. The read (RD#) control signal is also activated in T2 .The read (RD#) signal causes the addressed device to enable its data bus drivers. After RD# goes negative, the valid data is available on the data bus. The addressed device will drive the READY line high, when the processor returns the read signal to high level, the addressed device will again enables its bus drivers.
section .text global _start _start: smsw eax ;Reading CR0
bt eax,0 ;Checking PE bit(LSB), if 1=Protected Mode, else Real Mode jc prmode disp rmodemsg,rmsg_len jmp nxt1
prmode: disp pmodemsg,pmsg_len
nxt1: sgdt [gdt] sldt [ldt] sidt [idt] str [tr]
mov bx,[gdt+4] call disp_num
mov bx,[gdt+2] call disp_num
mov bx,[gdt] call disp_num
disp ldtmsg,lmsg_len mov bx,[ldt] call disp_num
mov bx,[idt+4] call disp_num
mov bx,[idt+2] call disp_num
mov bx,[idt] call disp_num
mov bx,[tr] call disp_num
mov bx,[cr0_data+2] call disp_num
mov bx,[cr0_data] call disp_num
disp nwline,1 exit: mov eax,01 mov ebx,00 int 80h
disp_num: mov esi,dnum_buff ;point esi to buffer
mov ecx,04 ;load number of digits to display
up1: rol bx,4 ;rotate number left by four bits mov dl,bl ;move lower byte in dl and dl,0fh ;mask upper digit of byte in dl add dl,30h ;add 30h to calculate ASCII code cmp dl,39h ;compare with 39h jbe skip1 ;if less than 39h skip adding 07 more add dl,07h ;else add 07 skip1: mov [esi],dl ;store ASCII code in buffer inc esi ;point to next byte loop up1 ;decrement the count of digits to display ;if not zero jump to repeat
disp dnum_buff,4 ;display the number from buffer ret
mov esi,char_sum+7 ; load last byte address of char_sum buffer in esi mov ecx,8 ; number of digits
cnt: mov edx,0 ; make edx=0 (as in div instruction edx:eax/ebx) mov ebx,16 ; divisor=16 div ebx cmp dl, 9 ; check for remainder in EDX jbe add30 add dl, 07h add30: add dl,30h ; calculate ASCII code mov [esi],dl ; store it in buffer dec esi ; point to one byte back
dec ecx ; decrement count jnz cnt ; if not zero repeat
print char_sum,8 ; display result on screen ret ;———————————————————–
mov esi,char_count+7 ; load last byte address of char_count buffer in rsi mov ecx,8 ; number of digits
cnt: mov edx,0 ; make rdx=0 (as in div instruction rdx:rax/rbx) mov ebx,16 ; divisor=16 for hex div ebx cmp dl, 09h ; check for remainder in RDX jbe add30 add dl, 07h add30: add dl,30h ; calculate ASCII code mov [esi],dl ; store it in buffer dec esi ; point to one byte back
dec ecx ; decrement count jnz cnt ; if not zero repeat
print char_count,8 ; display result on screen ret ;———————————————————–